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Lattice Semiconductor Plans SRIO Interoperability with Cavium Networks’ OCTEON II Processors

HILLSBORO, OR - MAY 11, 2010 - Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced plans to interoperate between Cavium Networks’ (NASDAQ: CAVM) OCTEON® II CN63XX processors and the LatticeECP3™ FPGA family via a Serial Rapid IO (SRIO) Specification 2.1 link. SRIO is commonly used in 3G/4G wireless base stations and wireline switches and routers where low latency is critical. Cavium’s OCTEON II processor incorporates two to six cnMIPS64® cores, the most advanced third generation hardware acceleration, and SERDES-based I/Os, including SRIO. Lattice’s ECP3 device boasts the lowest power in a mid-range FPGA family, rich memory density, DSP blocks and SERDES I/Os capable of supporting SRIO.

Cavium and Lattice have already begun executing their plan to demonstrate SRIO interoperability, and both companies will announce updates as they become available. “The addition of the SRIO interface in the OCTEON II processors, along with the wide variety of other standards-based interfaces, provides a new low-latency connectivity option,” said Tasha Castańeda, Senior Strategic Alliance Manager, Cavium Networks. “We are pleased to add Lattice to Cavium’s PACE (Partnership to Accelerate Customer End-solutions) ecosystem in order to offer our customers a strong FPGA design solution.”

“Lattice is excited to be working with Cavium Networks. This SRIO interoperability testing will strengthen our rich portfolio of wireless IP. We are working to introduce future bridging applications for the OCTEON II and our ECP3 family, including SRIO to CPRI, SRIO to PCIe and SRIO to SGMII,” said Ted Marena, Director of Business Development for Lattice.


About Cavium Networks

Cavium Networks is a leading provider of highly integrated semiconductor products that enable intelligent processing for networking, communications and the digital home. Cavium Networks offers a broad portfolio of integrated, software-compatible processors ranging in performance from 10 Mbps to 40 Gbps that enable secure, intelligent functionality in enterprise, data-center, broadband/consumer and access and service provider equipment. Cavium Networks processors are supported by ecosystem partners that provide operating systems, tool support, reference designs and other services. Cavium Network’s principal offices are in Mountain View, CA with design team locations in California, Massachusetts, India and Taiwan. For more information, please visit: http://www.caviumnetworks.com.

About Lattice Semiconductor
Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions. For more information, visit www.latticesemi.com


Cavium Networks Contact:
Angel Atondo
Marketing Communications Manager
Cavium Networks
805 East Middlefield Road,
Mountain View, CA 94043
Telephone: +1 (650) 623-7033
Email:angel.atondo@caviumnetworks.com


Editorial/Reader Contact:
Brian Kiernan
Corporate Communications Manager
Lattice Semiconductor Corporation
Telephone: 503-268-8739
Fax: 503-268-8193
Email:brian.kiernan@latticesemi.com

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